it’s up to the chip designer to figure out how to accomplish it
Exactly, which is my point, and since RISC-V doesn’t have a specific chip designer, but the ISA is open, you can’t equal RISC-V ISA in general to any specific chip.
Yes, it would technically be like defining AMD to mean all x86 architecture. Sometimes it would have reflected well. Other times not. But never would have been accurate.
Hopefully though well see smart SIMD subsystems and vector units that can accelerate the operations. Without requiring new hard coded CISC microcode like modern x86. But only time will tell.
Exactly, which is my point, and since RISC-V doesn’t have a specific chip designer, but the ISA is open, you can’t equal RISC-V ISA in general to any specific chip.
Yes, it would technically be like defining AMD to mean all x86 architecture. Sometimes it would have reflected well. Other times not. But never would have been accurate.
Hopefully though well see smart SIMD subsystems and vector units that can accelerate the operations. Without requiring new hard coded CISC microcode like modern x86. But only time will tell.